1. Field of the Invention
The present invention relates to a dual-frequency matching circuit that enables impedance matching at two separate frequencies simultaneously, and more particularly to an improvement of the matching circuit that can be suitably used in the microwave band.
2. Description of the Related Art
FIG. 9 is a schematic diagram showing a conventional dual-frequency matching circuit cascaded with a field-effect transistor (hereinafter referred to just as an "FET", or an "FET transistor"), as disclosed in the "Dual-frequency matching technique and its application to an octave-band (30-60 GHz) MMIC amplifier" by NAKAJIMA, M, MURAGUCHI, in IEICE TRANS, ELECTRON., VOL.E80-C, No. 12, December 1997.
In the figure, reference numeral 1 denotes an input terminal of the matching circuit, numeral 2 denotes an output terminal of the matching circuit, numeral 47 denotes a transmission line provided between the input terminal 1 and the output terminal 2, numeral 48 denotes a shorted stub provided between the input terminal 1 and the transmission line 47, the length of which is a quarter-wavelength .lambda./4 at a high angular frequency .omega..sub.H, numeral 49 denotes an open stub provided between the input terminal 1 and the transmission line 47, and reference numeral 50 denotes an FET transistor, the gate of which is connected to the output terminal 2.
FIG. 10 denotes a Smith Chart for explaining the matching method in the conventional dual-frequency matching circuit. In the figure, reference numeral 51 denotes a load impedance generated in a case that a low-frequency signal f.sub.L is applied to the FET transistor 50, reference numeral 52 denotes an impedance generated in a case that a high-frequency signal f.sub.H is applied to the FET transistor 50, and reference numeral 53 denotes a constant conductance circle (a constant conductance circle of 0.02 S, for example).
First, by setting the length of the transmission line 47 to a predetermined length, the two impedances of the above-mentioned FET transistor are set on to the constant conductance circle 53. Reference numeral 54 denotes a thus obtained transformed impedance of the case that the low-frequency signal f.sub.L is applied, whereas the reference numeral 55 denotes a transformed impedance of the case that the high-frequency signal f.sub.H is applied.
Thereafter, by setting the length of the open stub 49 to a predetermined length, the above-mentioned two impedances are shifted along the constant conductance circle 53 so as to be matched with each other, and reference numeral 56 denotes a point at which they are matched. In this way, the conventional matching circuit enables an impedance matching at two separate frequencies f.sub.L and f.sub.H.
The operation of the above conventional dual-frequency matching circuit is as follows.
When a signal is to be input through the input terminal 1 to the EET transistor 50, no reflected wave due to the input signal is generated at the above two matching frequencies f.sub.L and f.sub.H.
Since the conventional dual-frequency matching circuit is configured as such, two input impedances of the FET transistor 50 at two different frequencies are transformed on to the constant conductance circle 53 only on the basis of the length of the transmission line 47, so that if the length of the transmission line 47 is determined in such a manner that an impedance at one of the two frequencies is shifted on to the constant conductance circle 53, the other frequency at which the impedance can be shifted on to the constant conductance circle 53 is automatically determined, so that there has been a problem that the matching of impedances at two arbitrarily selected frequencies is not made possible.
Further, as a transmission line 47 is adopted in the conventional dual-frequency matching circuit, if the matching is to be performed in a low-frequency band, a considerably long transmission line is required, so that the size of the frequency-matching circuit as a whole is also made too large.